Table III-1
|
Pin # |
Row z |
Row a |
Row b |
Row c |
Row d |
Row e |
Row f |
|
1 |
COM |
+5 V |
+5 V |
+5 V |
+5 V |
+5 V |
COM |
|
2 |
COM |
RET_WX |
RESERVED |
+5 V |
TBUS1+ |
TBUS1- |
COM |
|
3 |
COM |
RET_WX |
RESERVED |
RESERVED |
TBUS2+ |
TBUS2- |
COM |
|
4 |
COM |
Vw |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
5 |
COM |
Vw |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
6 |
COM |
RET_WX |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
7 |
COM |
AREF_WX |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
8 |
COM |
RET_WX |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
9 |
COM |
Vx |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
10 |
COM |
Vx |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
11 |
COM |
Vy |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
12 |
COM |
Vy |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
13 |
COM |
RET_YZ |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
14 |
COM |
AREF_YZ |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
15 |
COM |
RET_YZ |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
16 |
COM |
Vz |
RESERVED |
USER I/O |
USER I/O |
USER I/O |
COM |
|
17 |
COM |
Vz |
RESERVED |
RESERVED |
TBUS3+ |
TBUS3- |
COM |
|
18 |
COM |
RET_YZ |
RESERVED |
RESERVED |
TBUS4+ |
TBUS4- |
COM |
|
19 |
COM |
RET_YZ |
RESERVED |
RESERVED |
TBUS_OC1 |
TBUS_OC2 |
COM |
Notes:
1. AREF_WX, AREF_YZ, all RESERVED and all USER I/O pins are unbussed feed-throughs that do not connect to any backplane planes or signal lines.
2. Vw, Vx, Vy and Vz are extra power pins whose voltage is determined by the system integrator. Vw and Vx share a common return plane RET_WX. Vy and Vz share a common return plane RET_YZ. RET_WX and RET_YZ are isolated from each other and all other returns.