Wednesday Trigger Group Meeting Notes.

The usual cast of characters is: Erik Gottschalk, Mike Wang, Xiaonan Li, Mike Haney, Dave Berg, Vince Pavlicek, Gustavo Cancelo, Greg Deurling, Ken Treptow, and Ted Zmuda.
There is not an official person keeping these minutes so there are gaps occasionally, sorry.

11 July 2002

• Terra Soft Solutions presented their newest blade product, the Moonlight Dual G4. Plenty of power, a lot of peripherials and a possible use in the Track and Vertex farm. See the data sheets and specs for details but here are some of my nome notes: Verticle airflow, no fan, needs external fans. PMC slot for Rapid I/O port or custom interconnect, i.e. incoming data path, two Gigabit ethernets for level1 buffers and GL1 connection. Rack of blades includes a switch which could collect GL1 messages. A quick write up of the cost estimate of a track and vertex processor made from these blades is here as a Word document.

Large Gap.....

18 and 25 July 2001

• Most of the discussion involves the DSP prototype designs (mother and daughter cards) which are moving along. As discussions of how the cards will be used progress improvements to the design are siggested.  An input FIFO is added when it is realized that the FPGA/buffer on the input stream can only hold 1.5 average events. The added FIFO can hold 4 average events. Gustavo also presents the latest queue simulations.  He shows that communicating negative results between the processing elements doing a single BB33 stage (3 half stations) reduces the internal FIFO sizes almost a factor of ten.  Ted will be looking at how this communication is implemented and how much silicon is needed but the memory saved is large enough that it should be a winner none the less.  Mike Wang taked about DSP code size and the difficulties of profiling the code when it is too big to reside in internal or even local cache.  Mike is looking forward to the 64xx processors.

21 Mar 2001

• As a result of the NSF ITAR proposal discussions, data rates were questioned. There was an attempt to gather the dispirate data on rates to help identify trouble spots. An EXCEL spreadsheet is in progress.

7&14 Mar 2001 were a lot of WBS discussions.

21 Feb 2001

• The design needs an input capability for standard data sets to be able to run algorithm comparisons. The data should be able to be introduced at several places in the processing stream.

14 Feb 2001

• Serial port on the TI DSPs has a 100 MHz clock. It is not an RS-232 port.

7 Feb 2001

• More numbers. Hits/BCO = 17.7, tracks/BCO = 5.2, hits per track = 3.4
• Event size is 24.7 pixels per half plane per half plane and 12.4 KBytes for the whole detector.
• At 132 ns that is 92 GByte/sec

2 Feb 2001

• Discussion of pixel readout board and shinge specific links. Discussion of the possibility of the pixel readout board replicating data at a quadrature overlap so that both quadrant processors have the hits.

17 Jan 2001

• My notes say L1 Buffer data rates of 1 Gbyte per second. No calculation shown.
• Another number. 7 MHz times 2500 DSP processors yields an average latency of 357 microseconds. Really 132 ns X 2500 = 330 microsec. With enough buffer we should be able to have a maximum of 50 milliseconds L1 trigger decision latency.

16 Jan 2001 - Full group meeting

• DAQ group discussions bring up the need for a time slot organizer so that early trigger decisions are put back in bunch crossing numerical order with delayed decisions.

20 Dec 2000

• Event ordering must be done at or before the L1 buffer. At trigger buffer timeout a tag should be entered into the L1 buffer. Data after that can be processed in L2/3 but it will be marked that it was not used in L1. Trigger buffer logic should be able to detect and report late data arrivals.
• The limit on late events is the bunch crossing counter in the pixel readout chip. It is 8 bits. Will it count modulo 159??
• 159 bunches per turn x 132 ns per bunch = 21 microseconds per turn = timeout.

13 Dec 2000

• The pixel size is 50 by 400 micrometers. When the cluster finding generates hit information it will have about 50/4 or 12.5 micrometers of resolution on a 10 centimeter pixel plane. requires 1 part in 8000 or 13 bits of x-y resolution. Add maybe a sign bit so the beam is 0,0. Decision that x and y position information will be 16 bits for each. The upper bits could be tag bits identifying seed regions. This seed info could be included in the translation tables.

15 Nov 2000

• Hit rate estimated at 16 track hits per plane.
• Pixel chip IDs will probably be added off the detector.

Notes from the Nov. 2000 Electronics Workshop.

Milestones for Feb 2002:

• DSP software running on prototype hardware
• Completion of an algorithm timing study to support the number of processors needed.
• Completion of a queuing analysisof the pixel processor and FPGA tracker to define data flow quantities.
• Prototype pixel processor and FPGA tracker by summer 2001.
• Definition of the Contro/Initialization/Monitoring fabric interconnecting the DSP farm.