Acronyms (up to VRB and VFO) 

ADC- Analog to Digital Converter. Also A2D.

AS* - The address strobe signal on the VME bus. The falling edge signifies valid address data on the bus. The slave latches this data on the rising edge of AS*.

ASIC – Application Specific Integrated Circuit. The SVX2 and SVX 3 chips are ASICs.

BE – General use acronym for Back End. Applied to clocks and to the parts of the SVX2/3 chips.

BN – General use acronym for Bottom Neighbor. Applied to data passing between SVX3 chips.

CPC – Compact (or Ceramic) Port Card. the implementation of the Port Card which is designed for use in the final detector system. This implementation is done using hybrid mounting technology and fancier materials in order to reduce mass. It is not likely to be seen in any engineering test stands except under controlled circumstances. See DPC.

CDF – Collider Detector at Fermilab. (You knew that, right?) At B0.

D0 – The other collider experiment. At D0 (amazing).

DAQ – Data Acquisition System. Sometimes applies to the control software the controls the SVX system. But can apply to all the software and hardware from the detector to the VRBs.

DDR – Digital To Analog Converter/Decoder/Regulator chip. Provides support for the front end chips by 1) regulating some key voltages, 2) generating calibration voltages, 3) clock buffering and 4) decoding some control commands and helping with initialization and data readout. FNAL designed chip.

DEM – Data emulator. See SVX MODULES

DOIM – Dense Optical Interface Module. The radiation hard fiber optic link modules that move the data bytes from the detector to the FIB subrack. There is a transmitter and receiver module and the fiber optic cable connecting them is a nine fiber ribbon.

DPC – Discrete Port Card. One particular implementation of the Port Card, done in normal FR4 & copper printed circuit board techniques. The DPC is meant for use only in test stands and not in the final system. See CPC.

DPM – Dual Port Memory. Memory that can be read from or written to by two controllers simultaneously.

DS0*, DS1* - The data strobe signals on the VME bus. The falling edge signifies valid data information on the bus. The slave latches this data on the rising edge of DS0/1*.

DTACK – Data Acknowledge. A VME bus signal that is the slave acknowledging a transfer back to the master.

EOR – End of Record. A fixed bit pattern added to the data stream by the FIB that indicates the end of the record.

FE – General use acronym for Front End. Applied to clocks and to the parts of the SVX2/3 chips.

FIFO – First-in-First-out. A type of memory used to temporarily store information. The value of the part is in maintaining the order of the information while allowing different clock rates at the input and output.

FFO – FIB Fan Out. Occasionally called a FOB or Fan Out Board. See SVX MODULES

FIB – Fiber Interface Board. See SVX MODULES

FPGA – Field Programmable Gate array. A programmable logic device as opposed to using fixed logic with standard family devices. (TTL, CMOS etc.). Also PLD.

FTM – FIB Transition Module. See SVX MODULES

G-Link – Gigabit Link, I think. A fiber optic, high speed communication link. HP and Finisar make the products used in the SVX system.

GRT – The original VTM. There is one GRT somewhere around the ESE test stand area.

GSTM – General System Test Module. See SVX MODULES.

HDI – High Density Interconnect. A flexible cable connecting a detector ladder to a Port Card. One Port Card connects to five HDIs.

ISL – Intermediate Silicon Layer. The next layer of the detector onion outside of the SVX detector.The data acquisition for this detector will use much of the same hardware as SVX.

ISP – In-System Programmability. The ability to load new firmware into programmable logic parts without removing said parts from the boards. Implemented in the GSTM, FIB and FFO.

JTAG – A protocol for loading the firmware into FPGAs. Developed by the Joint Test Action Group because it is also used to load test signals for chip boundary testing. Usually used to describe the port on a module where the connection is made when one is loading firmware into the modules FPGAs.

L1A – Level One Accept. A signal indicating that the trigger system thinks this data is good enough to be saved for the level two processing.

LCDS – Low Current Differential Signaling. A type of digital logic signaling designed by FermiLab.

LVDS – Low Voltage Differential Signaling. A type of digital logic signaling designed by Texas Instruments.

MBLT – Multiplexed Block Transfer. A VME64 mode that uses all the data and address lines at the same time to do 64 bit transfers over the VME bus. Usually called D64 mode.

MC/TSI – Master Clock / Trigger Supervisor Interface adapter. See SVX MODULES

OBDV – Odd Byte Data Valid. The data from the Port Cards is nine bits wide. There are eight data bits (a byte) and a "clock", OBDV. The transitions on OBDV occur during the valid data time of the data bits.

PLD – Programmable Logic Device. Also FPGA.

PIPE-RD1 and 2 – Signals that move the charge in the detector silicon to the different levels of processing in the SVX3 chips.

RBERT – Receiver card of the XBERT family. See XBERT.

SRAM – Static Random Access Memory. Usually volatile and loses contents on a power cycle.

SRC – Silicon Readout Controller. See SVX MODULES

STAR – Silicon Test Acquisition and Readout module. Sort of a beta SRC. Works with TFIB and DPC.

SVT – Silicon Vertex Tracker. Part of the trigger system for CDF, it will look for secondary vertices. Detector data is sent here as well as to the VRBs for recording.

SVX – Silicon Vertex Detector. One of the detector subsystems in the CDF detector. The inner layer of the onion. Provides particle track information. Built of layers silicon strips. Particles passing through leave charge trails. The charge is collected and digitized in the detector and the values are brought out through the SVX DAQ to the counting room. SVX II is the upgrade to the original SVX detector. SVX2 and SVX3 are the FNAL designed digital/analog chips that collected and digitize the data.

TAXI – Transparent Asynchronous XCVR Interface. An AMD designed point-to-point communications link at up to 100Mbps. Advanced Micro Devices supplies a chipset that implements this link.

TBERT – Transmitter card of the XBERT family. See XBERT.

TFIB – Test FIB. The first generation FIB. Still used for ladder testing with a STAR.

TN – General use acronym for Top Neighbor. Applied to a token connection passing between SVX3 chips.

TSI – Trigger Supervisor Interface. See SVX MODULES

VFO – VRB Fan Out. See SVX MODULES

VRB – VME Readout Buffer. See SVX MODULES

VTM – VRB Transition Module. See SVX MODULES

XBERT – General purpose Bit Error Rate testor. Consists of a PBERT and some number of TBERTs and RBERTs. The PBERT host card plugs into an ISA slot of the PC that is controlling the BERT system. It can control up to four RBERT/TBERT pairs.

NOT DEFINED: Byte, CMOS, CPU, DIN, ECL, EMI, ESD, IC, ID, IEEE, Kb, PCB, PECL, TTL.
 

GSTM – General System Test Module. A 9U VME module that is used to emulate SVX modules. It allows debugging a module without having the other modules that it interfaces with. The GSTM can accept up to four adapter modules (two transmitters and two receivers) that emulate some signal source or destination.
 

GSTM Adapters.

DEM – Data emulator. Transistion card. Plugs into the back of a FIB (replaces the FTM) and provides emulated detector data on up to ten channels.
 

FIB family. The FIB subracks are down in the collision hall.

SRC – Silicon Readout Controller. 9U module, Harvard Controls the SVX DAQ system. Synchronizes to the accelerator master clock. Accepts commands from the CDF trigger system (TSI). Gives commands to the FIBs and VRBs.

TSI – Trigger Supervisor Interface. 9U module, Michigan? The trigger system module that communicates trigger information to the detector subsystems.
 

VRB Family. The VRB subracks are up in the counting room.

 Under Construction. You can help. Send information or acronyms to the author, vince@fnal.gov .