D. initialization bits as used by George Pope
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FE max SHIFT REGISTER BIT ASSIGNMENTS (in order of loading):

Channel mask             127-0             alternating
Cal_Dir                         0 or 1 *
Polarity SEL                  0 or 1 *
Preamp BW 0-2                 2
Pipe delay 0-5                 40 (for 132ns operation)
ISEL 1-11    int. input bias     5
        int. reset bias                   0
        pipe write bias                 3
        pipe read bias                  3
Readout order PB                 0 or 1 *

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M63D MIN SVX3B Shift Register Bits

Chip ID[MSB(35):LSB(41)]         31
Not Used                                         0
Bias Ratio Select                              0
Driver Common Mode Select          0
Last Chip                                         1
ReadNbrs                                         0
ReadAll                                             1
Ramp Up/Down                             0 or 1 *
Comp Up/Down                             0 or 1 *
Ramp Cap Adjust[LSB(21):MSB(28)]    120
Threshold[LSB(13):MSB(20)]                 0
Counter Modulo[LSB(5):MSB(12)]        250
Ramp Pedestal[MSB(1):LSB(4)]             7

* = see section C on polarity bits