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SVX3FE Shift Register Bits
Jan. 27, 1997
Tom Zimmerman
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Channel masks 127 -- 0     (NOTE reverse channel mask order from SVX2)
Cal Dir
Pipeline SEL
BW 0-2
Pipe Delay 0-5
Pipe Read Bias 0-1
Pipe polarity (PB)

Total = 142 bits for the front end.

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SVX3B Shift Register Bits
Rev 1.2 20 JAN. 1997 
Oren Milgrome
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(Bit 1 is closest to SR Input, loads last)
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TNBR ->    
1-4	Ramp Pedestal[MSB(1):LSB(4)]
5-12	Counter Modulo[LSB(5):MSB(12)]
13-20	Threshold[LSB(13):MSB(20)]
21-28	Ramp Cap Adjust[LSB(21):MSB(28)]
29	Comp Up/Down
30	Ramp Up/Down
31     	ReadAll
32	ReadNbrs
33	Last Chip
34-41	Chip ID[MSB(34):LSB(41)] LSB is
	not set to FIFO, but is in SR 
-> BNBR
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