1/28/97 

First some conventions.

BE -> refers to the SVX-3BE chip, 'BE' is for 'back-end'.  This chip has
	the digital functionality of the chip set.

FE -> refers to the SVX-3FE chip, 'FE is for 'front-end'. This has the 
	analog amplifer, pipeline, and deadtimeless skip-logic.

Hybrid -> one side of a "butterfly" circuit layout that would service
	  either the r-phi side or the z-side of the chips.

************************************************************************
The following are guidlines that should be followed whenever possible in
designing the layout of the hybrid. These guidelines are based on the 
results of tests performed by Tom Zimmerman from 8/96-10/96.
************************************************************************

1). Ideally there should be one very large bypass capacitor 
	(greater than 1uf) per hybrid pair for AVDD and AVDD2. the existing 
	hybrid set for layer 0 seems to only have space for one capacitor 
	of this size, in that case connect the capacitor to AVDD2.

2). DVDD of the FE chip should NOT be connected to DVDD of the BE chip.
	All of the following FE chip power pads should go to the same
	0.1uF bypass per chip (for layer 0 this means four caps):
	AVDD
	PVDD
	DVDD
	QVDD

4). QVDD and AVDD on the SVX-3BE chip should connect to the 
	same point as all of the pads mentioned in the previous
	rule.  In the case of the SVX-II hybrid we will be supplying
	only 3 voltages to the hybrid. AVDD2, Analog Power, Digital
	Power. In this case the table below details which pads 
	should be connected to these power feeds.
	
	     Pad Name     |AVDD2|  Analog Power  |Digital Power  |
	------------------|-----|----------------|---------------|
	   (FE) AVDD2     |  X  |                |           	 |
	   (FE) AVDD	  |	| 	X	 |		 |
	   (FE) PVDD	  |	|	X	 |		 |
	   (FE) DVDD	  |	|	X	 |		 |
	   (FE) QVDD	  |	|	X	 |		 |
	   		  |	|		 |		 |
	   (BE) AVDD(AREF)|	|	X	 |		 |
	   (BE) QVDD	  |	|	X	 |		 |
	   (BE) DVDD	  |	|		 |	X	 |
	------------------|-----|----------------|---------------|
	  


5). NWELL should connect to an 0402 physical size capacitor in the 
	gap (or on the sides) between chips. The NWELL line should then
	run through a resistor to AVDD (the same point as above). This
	creates a low-pass filter for the NWELL line.

6). AVDD2 should have it's own 0.1uf capacitor as close to the bond pad 
	as possible. This is for each FE chip.

7). There should be one common ground plane for the chip sets
	on the hybrid. This ground plane is what the 
	back face of the chip rests upon. ALL ground pads (on both the 
	FE and BE chips) should be wire bonded to this ground plane.

8). for hybrids that require bonding in the gap between chips (hybrids
	that are not for layer 0), a 54mil gap is required between the 
	chips minimally.

9). ISET1 should be bypassed to ground. ISET2 bypassed to AVDD.
    ISET1 conn. to a resistor to AVDD.	ISET2 connects to a resistor to GND
    
10). FE_clk and FE_clk* (this is also true for BE_clk and BE_clk*) 
	should be differentially terminated once per hybrid pair
	to the characteristic impedance of the control cable.
	We expect this impedance to be 80-100 ohms differential.