SVX J3 Backplane

• 1. GENERAL INFORMATION
  • 1.1 System Introduction
  • 1.2 Description Of Component & How It Fits Into The System
  • 1.3 List Of Component Requirements
• 2. THEORY OF OPERATION AND OPERATING MODES
  • 2.1 Basic Features & Operation
  • 2.2 Diagnostic Features
• 3. Interface Specifications
  • 3.1 Local TTL Bus Physical Interface
  • 3.2 TTL Bus Protocol
  • 3.3 Receiver Connector and Driver Connector Pin-out
• 4. FIB/VRB Custom J3 Backplane Technical Appendix
  • 4.1 Specific Details of Controlled-Impedance Clock Fanout Wiring on FIB/VRB Subrack Custom J3 Backplane
  • 4.2 Mechanical Mounting and Connector Placement Information
  • 4.3 Schedule Estimate

SVX II Silicon Strip Detector Upgrade Project

Readout Electronics for Beam Test

VRB/FIB Custom J3 Backplane

--PRELIMINARY--

June 17, 1996

REVISED September 4, 1996

REVISED October 18, 1996

John T. Anderson

Kerry Woodbury

Document # ESE-SVX-960130

1. GENERAL INFORMATION

This document specifies the construction and design of a J3 backplane for use in the 9U X 400 mm VME subracks that contain the FIB and VRB boards.

1.1 System Introduction

(SVX II Silicon Strip Detector Upgrade Project Readout Electronics VRB/FIB Custom J3 Backplane -

add general description of readout electronics and general descriptions of FIB and VRB sub-systems).

1.2 Description Of Component & How It Fits Into The System

Each VRB and FIB subrack requires the use of a separate 21-slot backplane of which 13 slots are used for special VRB and FIB purposes and 8 slots are reserved for user I/O. This backplane is used for inter-module communication and for low-skew clock distribution.

1.3 List Of Component Requirements

The VRB/FIB Custom J3 backplane shall meet the following requirements:

• Mechanical compliance with Eurocard specifications for a 3U height backplane.

• Width to accommodate 21 module positions.

• 12 Receiver slots which shall use the 5-row, 235-pin, 2mm pin pitch J3 connector constructed from AMP 2mm Hard Metric components or exact equivalent.

• A single Driver slot which shall use the 5-row,235-pin, 2mm pin pitch J3 connector, constructed from AMP 2mm Hard Metric components or equivalent.

• Eight user-defined slots which shall be capable of using the 5-row, 160-pin DIN J3 connector.

• Low-noise, multi-layer, strip-line construction for controlled impedance and signal propagation delay.

• Be routed to provide clock distribution from a central slot to all other slots with less than ±100 psec skew between any two slots. The skew between any MCLK and SYNC pair shall further be limited to ±100 psec from MCLK to SYNC.

• Be routed to provide a 25-bit TTL bus for inter-module communication. This TTL bus shall be driven by drivers that conform to the VME64 specification and terminated in an impedance equal to that of the standard VME backplane as defined in the VME64 specification.

• Provide connections from the Driver slot for power and ground to supply termination networks attached to the aforementioned 25-bit TTL bus.

• Backplane thickness in accordance with IEEE standards 1101.1 and 1101.10.

• Three unique traces, SLAVE_READY, RESERVEDA, and FINISHED, are provided for a separate, assumed slow, user TTL bus which connect pins C8, C9 and C10 of slot 4 to pins C45, C46 and C47 of slot 15, respectively.

2. THEORY OF OPERATION AND OPERATING MODES

2.1 Basic Features & Operation

The VRB/FIB Custom J3 Backplane provides an interconnect between the FIB module, the VRB module and their associated transition modules. The J3 backplane incorporates a 25-bit TTL bus for data transmission and traces for the fan-out of two ECL differential clocks. FIB and VRB modules are only installed in slots 9-21 of the VME subrack, with slots 1-8 reserved for user and system control modules. The Custom J3 Backplane is manufactured with connectors for Transition Module attachment in all positions but the area for user and system modules contains no wiring of any form with the exception of SLAVE_READY, RESERVEDA and FINISHED described above. A sketch of the finished backplane in shown below as Figure 1.

To provide for user configuration, no copper traces or planes, with the exception of the three traces which run from slot 15 to slot 4, shall extend closer to the slot 8 connector that the line 0.100" to the left of the ‘z’ row of the slot 9 connector, as viewed from the Module (front) side of the subrack. This allows the user, if necessary, the ability to shear off the 8-slot blank portion of the VRB/FIB Custom J3 Backplane and replace it by their own custom backplane for slots 1-8 without damaging the major electrical characteristics of the VRB/FIB Custom J3 Backplane. Shearing the backplane will, of course, cut the three traces which run from slot 15 to slot 4.

Varying connector types are used in the VRB/FIB J3 Custom Backplane. Slots 1-8 of the backplane are drilled for 5-row DIN connectors, but filled with 3-row DIN connectors. Slots 9-21 are filled with 235-pin, 5-row, 2mm pin pitch hard metric connectors.

Conceptual view of J3 Backplane

The VRB/FIB Custom J3 Backplane is a six-layer printed circuit board which mixes micro-strip (i.e. trace over single return plane) and strip-line (i.e. trace buried between two return planes) construction. The TTL bus is a micro-strip layer which is separated from the high-speed clock distribution by the arrangement of return planes. Strip-line construction is used for the high-speed clocks in order to maintain a consistent impedance. The layer stacking for the backplane is given in Figure 2.

Layer Stacking for FIB/VRB backplane

2.2 Diagnostic Features

The VRB/FIB J3 Custom Backplane has no built-in diagnostic features.

3. Interface Specifications

The VRB/FIB Custom J3 Backplane provides the physical interface between FIB and VRB modules. The protocol is specific only to these modules and is not designed to be extended outside the subrack. The general layout of the backplane is such that a TTL bus crosses all module slots, and a special clock distribution scheme sends two ECL differential clocks from slot 15 to all other slots. The clock distribution scheme requires that unique traces be used for every slots’ clock signal in order to minimize skew.

3.1 Local TTL Bus Physical Interface

A 25-bit TTL bus runs across all 13 populated positions of the VRB/FIB Custom J3 Backplane. One pin-out (hereafter called the Receiver pin-out) is found in slots 9-14 and 16-21. The other pin-out (hereafter referred to as the Driver pin-out) is found only in slot 15. Slots 1-3 and slots 5-8 have no special pin-out; in these slots all pins in all rows are User I/O and are non-bussed and unconnected to the backplane.

Three unique traces (SLAVE_READY, RESERVEDA and FINISHED) are provided for a separate, assumed slow, user TTL bus which connect pins C8, C9 and C10 of slot 4 to pins C45, C46 and C47 of slot 15, respectively.

3.2 TTL Bus Protocol

The protocol and timing of the local TTL bus is described in both the FIB and VRB specifications. The two modules use the same pin-out in different manners, as described in their respective specification documents.

3.3 Receiver Connector and Driver Connector Pin-out

The Receiver pin-out is as given in Table 1. Pins labeled as ‘USER I/O’ may be used as local interconnect between the Module and its associated Transition Module. Pins labeled as ‘RESERVED’ may not be used and shall be implemented in the backplane as non-bussed feed-throughs. Modules and Transition Modules shall not connect to RESERVED lines as they may be utilized in future revisions of the backplane.

The SYNC(n) and MCLK(n) signals correspond to the two differential ECL clocks which fan out from the Driver in slot 15 to slots 9-14 and 16-21. The connector in slot 9 will connect to SYNC9 and MCLK9, slot 10 provides access to SYNC10 and MCLK10, etc. The pinout of the Driver slot is given in Table 2. Table 3 provides a cross-reference showing which pins of slot 15 are connected to other slots in the backplane.

4. FIB/VRB Custom J3 Backplane Technical Appendix

This appendix details the technical requirements necessary for construction of the FIB/VRB custom J3 backplane. It is written as a series of items which are intended to be used as the basis for a purchase requisition.

1 The thickness of this custom J3 backplane shall conform to the IEEE 1101.1 and IEEE 1101.10 specifications.

2 The FIB/VRB Subrack requires the use of a separate 21-slot J3 backplane which shall be designed with only the rightmost 13 slots (slots 9-21) containing any traces or planes. The 8 leftmost slots (slots 1-8) shall be stuffed with connectors but shall contain no traces or planes. Figure 1, at the end of this section, shows a conceptual sketch.

3 This backplane shall be drilled, in slots 1-8, to accept the 5-row, 160-pin DIN connector. At assembly time, however, the 96-pin, 3-row connector shall be stuffed in to this drill pattern unless otherwise specified by the end user.

4 This backplane shall be drilled, in slots 9-21, to accept the 5-row, 235-pin hard metric, 2mm pin pitch connector without alignment/keying mechanics.

5 This backplane shall be of six-layer construction as detailed in Figure 2. No copper planes shall extend closer to the slot 8 connector than the line 0.100" to the left of the ‘a’ row of the slot 9 connector, as viewed from the Module side of the subrack.

6 Two of the six trace layers shall be used to route high-speed, low-skew differential clock signals in stripline form as shown in Figure 2. Layer ‘Signal 1’ shall be used to route the ‘+’ side of all differential clock signals and layer ‘Signal 2’ shall be used to route the ‘-’ side of all differential clock signals. The characteristic impedance, signal line to signal line, of the differential clock signal trace layers shall be 75 ohms, ± 10%.

7 The remaining signal layer of the backplane (Signal 3) shall be used to route a 25-bit TTL bus which runs from slot 9 to slot 21 inclusive. The three traces which run from slot 4 to slot 15 (SLAVE_READY, RESERVEDA and FINISHED) shall also be routed on this layer. The characteristic impedance of the single-ended TTL bus signal trace layer shall be 50 ohms, ± 10%.

8 All pins in all rows of all connector positions in slots 1-8 in the FIB/VRB Custom J3 Backplane shall be non-bussed feed-through pins designated for user I/O, with the exception of SLAVE_READY, RESERVEDA and FINISHED.

9 The total thickness of the VRB/FIB J3 Custom backplane shall be 0.093 inches± 0.003 inch.

10 All six copper layers shall be 1 oz. copper with a nominal copper thickness of 0.0015 inch.

11 The spacing between the GND and Signal 1 layers shall be 0.020 inch.

12 The spacing between the Signal 1 and Signal 2 layers shall be 0.020 inch

13 The spacing between the Signal 2 and +5 Volt layers shall be 0.020 inch.

14 The spacing between the +5 Volt and Signal 3 layers shall be 0.012 inch.

15 The spacing between the Signal 3 and GND layers shall be 0.012 inch.

16 All signals on the Signal 1 and Signal 2 layers shall be routed using 0.010 inch wide finished traces with a minimum copper-to-copper spacing of 0.080 ± 0.020 inch.

17 All signals on the Signal 3 layer shall be routed using 0.010 inch wide finished traces with a minimum copper-to-copper spacing of 0.040 ± 0.020 inch.

18 All connectors in slots 9-14, and slots 16-21, shall conform to the ‘receiver’ pinout given in.

19 The connector in slot 15 shall conform to the ‘driver’ pinout given in Table 2 - Driver Connector Pin-out. Pins labeled as ‘RESERVED’ shall be unbussed feed-through pins, as shall pins labeled ‘USER I/O’. Pins labeled with ‘MCLK’ or ‘SYNC’ connect to the high-speed differential clock signals as defined in the previous section. The pins labeled ‘GND’ shall be connected to the GND planes of the FIB/VRB Custom J3 Backplane and shall be cut short to preclude any connection to them by Transition Modules. The pin labeled ‘+5.0 V’ shall be connnected to the +5.0 Volt plane of the FIB/VRB Custom J3 Backplane and shall be cut short to preclude any connection to it by a Transition Module.

20 Pins 1 through 25 inclusive of the ‘b’ row, shall be individually bussed from slot 9 through slot 21 inclusive (e.g., pin 2 of row ‘b’, slot 9 to pin 2 of row ‘b’, slot 10, etc.) such that a 25-bit bus is formed running from slot 9 to slot 21, touching all slots in-between.

21 A termination network shall be installed in the FIB/VRB J3 Custom Backplane between slots 9 and 10 and between slots 20 and 21 such that all 25 bits of the bus described in the previous item see a termination to the +5.0 volt power plane and ground at both ends resulting in a termination impedance of 194 ohms ± 5% and an undriven voltage on the bussed line of 2.94 Volts, ± 10%, as shown in Figure 3 below.

Termination Network for TTL bus

22 The termination network described in (10) above shall be decoupled at each end (at slots 9 and 21) with the parallel combination of a 47 uF tantalum, surface mount, capacitor and a high-frequency surface-mount 0.1 uF capacitor. None of the components of the termination network shall shall extend closer to the slot 8 connector than the line 0.100" to the left of the ‘a’ row of the slot 9 connector, as viewed from the Module side of the subrack.

23 Rows ‘a’ & ‘e’ of the J3 connector shall be unbussed feed-throughs

24 Fermilab shall approve the artwork of the FIB/VRB Custom J3 Backplane prior to manufacture.

25 The minimum spacing between MCLK and SYNC signal traces in the Signal 1 and Signal 2 layers shall be 0.010".

4.1 Specific Details of Controlled-Impedance Clock Fanout Wiring on FIB/VRB Subrack Custom J3 Backplane

Rule 1. Slot 15 of the FIB/VRB Subrack Custom J3 Backplane shall interface to a control module which distributes clock signals originating from connector pins in slot 15 to slots 9-14 and slots 16-21 of the FIB/VRB Subrack Custom J3 Backplane. The pinout of the connector in slot 15 is given in Table 2 - Driver Connector Pin-out.

Rule 2. The SYNCn and MCLKn signals shall be connected from slot 15 to other slots as given in Table 3 - Driver Signals Routing Table. This table shows which pins of slot 15 carry the SYNC and MCLK signals to each of slots 9-14 and 16-21, and to which pins of slots 9-14 and 16-21 the signals are routed. All SYNC and MCLK signals are differential pairs, in which the ‘+’ side of the pair is routed on J3 backplane layer Signal 1 and the corresponding ‘-’ side of the pair is routed with an identical pattern, except at the end points, on J3 backplane layer Signal 2.

Rule 3. Trace lengths for all ECL signals from the sourcing pins of slot 15 to the destination pins of all slots shall be identical within ±5%.

Rule 4. Each SYNC and MCLK pair shall be routed with the same number of bends, in order to minimize skew, both between the signals in a pair and between the pairs themselves. The maximum allowable skew from any clock signal to any other clock signal shall be ±100 picoseconds.

4.2 Mechanical Mounting and Connector Placement Information

The J3 custom backplane will require mounting holes along the edges to allow the backplane to be mounted to the subrack. The mechanical drawings for the placement and size of these holes is pending delivery of this information from the subrack vendor.

Note that if the thickness of the J3 backplane is not the same as that of the J1/J0/J2 backplane, a spacer may need to be placed in the Transition Module side of the connector shroud to insure correct alignment and seating.

All connectors on the J3 backplane shall be evenly spaced upon a 1HP Eurocard pitch. The 2mm connectors require a different centerline offset than the DIN connectors. In addition, the offset from the board edge to the first slot position is, as of this writing, indeterminate. When specifications for the board edge to first slot position measurements are made known by the standards committee, a mechanical drawing specifying all connector placements will be provided.

4.3 Schedule Estimate

1 Specification updated: 6/1/96

2 Artwork contract: 6/15/96

3 Order Backplanes: 7/1/96