Below is a block diagram of the DCDM:
The DCDM is based on the Motorola MC68HC11 microcontroller, running in expanded bus mode, which features an external 8 bit data and 16 bit address bus. Additionally, the HC11 features an RS232 serial port and an 8 channel, 8 bit analog to digital converter. The system clock and bus run at 2.0 Mhz.
The HC11 can physically address 64kb of memory, which is divided into static RAM, ROM, EEPROM, and miscellaneous internal registers. Below is the memory map for the HC11 used in the DCDM:
The user 8kb RAM located at address $6000 is external to the HC11, as is the 16kb EPROM located at address $C000. Also, there are three registers located external to the HC11: the LCD register ($8000); the ISP register ($8001); and a general purpose register ($8002). Memory decoding is performed by a Lattice ISP2032, which is discussed in the next section.
The inputs to the memory decoder are the 6 least significant bits and the 4 most significant bits of the address, as well as Memory Read/Write control line (R/W*) from the HC11. Based on these inputs, various control signals are generated and used to select the external registers, ROM, RAM, and LCD for reading or writing.
In addition to providing memory decode logic, the Lattice ISP2032 contains an 8 bit write-only register (ISP REG) located at address $8001. Unused outputs of the ISP2032 (PAL[0:5]) are brought out to header J16 for future expandability.
When address $8002 is read the input bits to U8 are "seen" by the HC11. At the time of writing, only 5 of the 8 bits of this register are being used: bit 0 is the Start Button, and bits 1 through 4 are used to read the configuration toggle switches. The unused bits (GPIBIT[0:2]) are brought out to headers J14 and J12 for future expandability.
Writing to the display is a three step process. First, the data (either an ascii value or instruction) is written into the LCD register. Then, another write to the general purpose register sets up any extra control signals needed by the LCD module. Lastly, the LCD E bit is toggled though another series of writes to the general purpose register. See section 3.5 for more information about the LCD interface.
Due to the large number of analog voltages that need to be digitized, a system of multiplexers is utilized. A total of 80 lines are fed into 5 dual channel 8 to 1 multiplexers. These select lines are controlled directly by the HC11 via PORTA[3:5]. The 10 outputs of these multiplexers are fed into another series of 2 channel, 4 to 1 multiplexers. The select bits of this second set of multiplexers are directly controlled by the HC11 via PORTA[6:7].
Due to the fact that signals on the DART cables are differential, and that they multiplexers are wired in such a manner that
Because some of the termination networks have no external bias voltage, the DCDM incorporates pullup and pulldown resistors that can be enabled or disabled. Setting bit 0 in the internal ISP register enables the 2.2k ohm pullup and pulldown resistors, which connect to the outputs of the dual channel 8 to 1 multiplexers. Since the analog multiplexers have a low impedance, the pullup and pulldown resistors are effectively connected to the "floating" termination resistor. The multiplexer network is shown on page 2 of the schematic in appendix C.
The LCD contains a small microcontroller capable of writing ASCII values to the screen one character at a time, and also executing a small number of instructions. Some instructions are: clear screen, set cursor position, turn cursor on or off, turn screen on or off, and shift the display. After the LCD receives data, there is a short delay before new data can be accepted. This delay varies from 1.6ms for complex instructions such as initialize or clear screen to 40ms for most of the other instructions. When the LCD is again ready to accept data the "Ready" bit is set.
PC Board Construction
Size
Power Requirements
Cooling Requirements