BTeV Trigger at ESE 

 

These web documents are meant to closely track the ESE trigger documents at 'Eseserver0\share\ESE\Projects\BTeV\Trigger\Docs'. That is the working space and these are copies that are updated whenever significant changes are made. We have a proposal for the trigger meeting room beverage cooler .

Last updated: Apr. 26, 2001 by Vince Pavlicek

The Latest Draft of the Pixel trigger block diagram (could also be Muon trigger).

This includes the PTSM and GL1 systems. PDF or Word .


Global Level 1 documents.


Links to other places of interest.

DSP Prototype documents.  The latest on the prototype board.Oct2,2001

 


 

Trigger Hardware Group Meetings and presentations


WBS working documents and related administravia.

All the real WBS documents are at the BTeV cost and schedule pages.   Look there for the most current versions, guidelines, and example documents.

The current (depending on when it was updated) trigger group WBS working documents are:


Data Flow Analysis Technical Documents


Miscellaneous Technical Documents

Miscellaneous Presentation Documents

Documents generated as a result of the November workshop.

Documents from the November 2000 Workshop.

Workshop presentation of status of trigger implementation: Status as a Word file or Status as PDF Questions to be answered at the break-out sessions: Questions as a Word file or Questions as PDF .

This is a list of documents by Don Husby for the development of the BTeV Trigger

 

.doc

 

.pdf
 

 

 X 

 

 X 
Overview of pixel trigger architecture. This was written in Oct-99. It has a pretty good description of the basic architecture except that current plans call for the FPGA tracker to have a 4x4 switching backplane and the Farm-Box to have an 8x8 backplane. 

 

X
  The Farm-box is one of the major building blocks of the trigger system. 

 

X
  This describes the architecture of the FPGA tracker system. However, it does not describe the tracking algorithm. 

 

X

 

X
The Pixel processor does pixel formatting and translation. This document is fairly up to date. Current plans call for the delay buffer function to be implemented in a "standard" L1 buffer. However, the pixel processor will still have to do some time-sorting. There has been an ongoing debate about whether or not a center-of-mass calculation needs to be done. 

 

X
  This is two block diagrams implementing FPGA tracker algorithms. The first is the BB33 algorithm which has been simulated and advertised widely. It will be very difficult to implement. The second is much smaller, probably has better performance, but has yet to be simulated. 

 

X
  A short discussion of how to implement the Muon trigger using pixel-trigger hardware. Will Johns read this and commented that it was probably overkill. He thinks the trigger can be implemented using only one view from the detector. He should be the primary reference for this. 
 

 

X
Early talk (August, 1998) on the Systolic Associative trigger implementation. This was targeted to the triplet-based detector design and is the first to suggest reading out of track ends only. 

 

X

 

X
Update (July 1999) of the SAST algorithm to use the doublet detector design. 

 

X

 

X
SUMAC: Short description of the protocol used for the Serial Utility Monitor and Control system. 

 

X

 

X
Short discussion of software protocols for SUMAC 

Also, you can find some useful first generation information at the trigger prototype web page.

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