// Window access macros
#define MakeLong(Hi,Low) (((long)(unsigned)Hi << 16) | (long)(unsigned)Low)
#define Log_Area 38
#define W_Whole { CmdX=wherex(); window(1,1,80,ScreenH);   }
#define W_Cmdx  { window(1,Log_Area+1,80,ScreenH); gotoxy(CmdX,ScreenH-Log_Area);}
#define W_Cmd   { window(1,Log_Area+1,80,ScreenH); gotoxy(1,ScreenH-Log_Area); textattr(TEXT);}

#ifdef MULTI
enum { Enabled, Disabled, Fatal, Ready, Starting, Running };
#define W_Log   { CmdX=wherex(); window(2,20,79,Log_Area-1); gotoxy(1,Log_Area-20); }
#define W_Stat  { CmdX=wherex(); window(2, 2,79, 14);  }
#define W_Conf  { window(2, 16,79, 18);  }

#else
#define W_Log   { CmdX=wherex(); window(2,10,79,Log_Area-1); gotoxy(1,Log_Area-10); }
#define W_Stat  { CmdX=wherex(); window(2, 2,79, 4);  }
#define W_Conf  { window(2, 6,79, 8);  }
#endif

#define Plog1(T,V) { sprintf(Plog_S,T,V); Plog(Plog_S); }
#define Plog2(T,V1,V2) { sprintf(Plog_S,T,V1,V2); Plog(Plog_S); }
#define Plog3(T,V1,V2,V3) { sprintf(Plog_S,T,V1,V2,V3); Plog(Plog_S); }
#define BIT(N) (1L<<N)

// Device access macros

// Get current cycle count
#define Xcycle inpw(XBIO+8)
#define Rcycle inpw(XBIO)

// Current device status
#define Xstat  inpw(XBIO+10)
#define Rstat  inpw(XBIO+2)
// PC Status Register bit Assignment:
// Bits 3:0 are local to PC interface:
//  0001 Sempty	 No Status data received since last read.
//  0002 Rempty  No Register data received.
//  0004 Full	   Control link output FIFO is full
//  0008 C_err	 Control link got an error
//
// Bits 15:4 come from the remote module
//  00f0 Gpi[3:0] State of Gpi inputs
//  0100 Ready	  Link ready
//  0200 Lnk_Err  Link Error
//  0400 Si_Err	  Control Link Error at remote end.
//  0800 Cmp_Err  Compare Error
//  1000 Run	    Run/Idle state
//  2000 Dav	    Data available is asserted
//  8000 Error	  One of the Error bits is on.

// Get the results of a read request
#define Rdata  MakeLong(inpw(XBIO+6 ),inpw(XBIO+4 ))
#define Xdata  MakeLong(inpw(XBIO+14),inpw(XBIO+12))

// Device Writes - Send 32-bit Data to destination register
#define Send_Bert(Dev,Dest,Dat)  {   \
    outpw(XBIO+Dev  ,(unsigned int)(Dat));        \
    outpw(XBIO+Dev  ,(unsigned int)((Dat)>>16));  \
    outpw(XBIO+Dev+8, Dest); }

#define SendX(Dest,Dat)  Send_Bert(2,Dest,Dat)
#define SendR(Dest,Dat)  Send_Bert(4,Dest,Dat)
#define SendXR(Dest,Dat) Send_Bert(6,Dest,Dat)
#define SendM(Dest,Dat)  Send_Bert((XRmask<<1),Dest,Dat)
// Remote writeable registers
// 1   State    Set operating state
// 2   Config   Set clock configuration
// 4,6 Wram     Write to RAM (if 6, Inc Addr )
// 5,7 Cram     Compare to RAM (if 7, inc Addr)

// Remote readable registers
// 8   Echo     Send back what I send you
// 9	 Eword		Received word that caused an error (RBERT only)
// A	 Addr		  Send contents of Addr in bits 14:0  Freq in 19:16
// C,E Rram		  Read from RAM (if E, inc Addr)

// Lconfig register set local interface configuration
#define Lconfig(Dat) outpw(XBIO,Dat)
//	001 Break	 Reset remote modules - clear FPGA
//	002 Parity Disable parity - download FPGA
//	004 ErClr	 Clear Local Errors
//	010 Reset	 Clear local FPGA for reload
//  0e0 ChSel  Channel select
//  100 SetCh  Set Channel

// Remote register #2: configuration register
// 007f0000  Clock speed from 16.0 to 63.5mhz in .5mhz steps.
// 00003000  Receiver device select
// 0000001f  XTAL / KINV / ASYNC / DAV_HOLD / TWO_EDGE
// 00000100  X_RDY_POL Polarity of LINK_READY signal for TBert.
// 01000000  R_RDY_POL Polarity of LINK_READY signal for RBert.

// Remote register #1: State register bits
// 0001 Idle     Set device to Idle
// 0002 Run	     Start test
// 0010 ErClr	   Clear Errors
// 0020 AdClr	   Clear Addr register
// 0040 CyClr	   Clear Cycle counter
// 0080 GpoSet	 Set Gpo outputs
// 0f00 Gpo[3:0] State of Gpo outputs
// 1000 SoHold   Hold Serial link