MODULE Clock
@ALTERNATE;
" History
" Oct 96 Checksum=5204
" 13-Nov-97  Fixed DAVQ term from /Two_Edge*Rclk to /Two_edge+Rclk
"            Added more delay to RS_DELAY
"            CS=

RSTBK	   pin	1		;" Received strobe for clocking Flip Flops
RSTB	   pin	2		;" Rstb as an input pin
"          pin	3 unused
/DAV	   pin	4		;" Data Available
CK_SEL	   pin	5		;" Select RSTB (1) or XTAL (0)
DAV_HOLD   pin	6		;" Hold the DAV signal on first transition
TWO_EDGE   pin	7		;" Provide a pulse on each edge of RSTB
ASYNC	   pin	8		;" Do not synchronize transition from XTAL to RSTB
XTAL	   pin	9		;" 16MHz external crystal

RS_DELAY   pin 12		;" Delay RSTB for XOR edge detection
CLOCK	   pin 13		;" System clock output
RSDEL2   pin 14      	;" More RSTB delay
DAVQ	   pin 15		;" Latch DAV
Q1	   pin 16='pos,reg'	;" Synchronize clock select
Q0	   pin 17='pos,reg'	;"
FREQ	   pin 18       	;" Sent to frequency counter on FPGA
RCLK	   pin 19		;" Receive clock output.

equations

Q0 := CK_SEL			;" synchronize SEL
Q1 := Q0			;" synchronize SEL
CLOCK = XTAL;
FREQ = /RSTB;

RCLK =  XTAL*/CK_SEL * (ASYNC  +/Q0*/Q1) " Select crystal
     + /RSTB  * /ASYNC*Q0*Q1*(DAV+DAVQ)  " Synchronous enable of RSTB
     + ASYNC * CK_SEL *                  " Asynchronous enable
       (  RSTB * RS_DELAY	*(DAV+DAVQ)    " Catch the rising edge
        +/RSTB */RS_DELAY*DAVQ );        " Falling edge

" Note that RCLK stays low till DAV and the first rising RSTB
" DAVQ will transition after the first RCLK in 2-edge mode

DAVQ = DAV  * DAV_HOLD * (/TWO_EDGE + /RSDEL2)
     + DAVQ * DAV_HOLD * /ASYNC * Q0
     + DAVQ * DAV_HOLD *  ASYNC * CK_SEL;

RSDEL2   = /RSTB * TWO_EDGE;
RS_DELAY = /RSDEL2 * TWO_EDGE;

END