The XBERT is a general-purpose Bit Error Rate Tester for high
speed links. It can generate and check arbitrary data patterns
as large as 32K by 32 bits at speeds up to 63.5 Mwords/Sec.
The XBERT is a general-purpose Bit Error Rate Tester for high
speed links. It can generate and check arbitrary data patterns
as large as 32K by 32 bits at speeds up to 63.5 Mwords/Sec.
The Xbert manual is available in Microsoft Word 7.0 format or Adobe Acrobat (.PDF) Format
The WORD document is written using embedded hypertext links and is best viewed with Microsoft's Word Viewer. Right now, external links don't work well with Word version. Links don't work at all using Acrobat. Eventually, when word-to-www translation software is a bit more reliable, the document will be rendered as a real Web page.
Several XBerts have been running for several months.
We are preparing to build ~40 TTL Xberts for testing the Taiwanese
DOIM. These will go into single-high Eurocard racks.
Some modifications made to XBERT documentation including sample script files for the loopback test and the GLINKs.
The following schematics and source files are available. Be sure to set your pdf viewer to landscape mode when printing.
| RBERT | |
|---|---|
| Board Level Schematic | |
| Clock receiver PAL | |
| FPGA Schematics: | |
| RBERT | Top Level Schematic |
| RCMP | Comparator Pipeline. |
| CMP_REG | Comparator register primitive. |
| SERIN | Serial input port (Control Link). |
| SEROUT | Serial output port. |
| TTL Xbert Board-level |
|---|
| Tbert Schematic |
| Tbert PCB layout |
| Rbert Schematic |
| Rbert PCB layout |
| Pbert Schematic |
| Pbert PCB layout |
| Serial Control Link PAL |
|---|
| TBERT | |
|---|---|
| Board Level Schematic | |
| FPGA Schematics: | |
| TBERT | Top Level Schematic |
| SERIN | Serial input port (Control Link). |
| SEROUT | Serial output port. |
| PBERT | |
|---|---|
| Board Level Schematic | |
| ISA Address Decode Pal | |
| FPGA Schematics: | |
| PBERT | Top Level Schematic |
| SERINH | Serial input port (Control Link). |
| SEROFIF | Serial output port with FIFO. |
| External Documents | ||
|---|---|---|
| 65K | Astec power supply | |
| 727K | Cache ram chip | |
| 312K | Maxim RS-485 chip | |
| 326K | PLL clock generator | |
| 326K | ECL G-Link chip specification | |
| 326K | TTL G-Link chip specification | |
| 326K | IDT 74F3384 Bus Switch | |
| 3.5M | ORCA OR2C06 | |
| 326K | Lattice 16L8 GAL | |
| Software | |
|---|---|
| Xbert.zip | Executables |
| Xbert.c | Main source code. |
| Box.c | Routines for drawing boxes and menus. |
| Xbert.h | Include file for register definitions. |
| Box.h | Box include file. |
| Bit2brt.c | Source code for fpga bit-file converter |
