FPIX1 Inner Board for Test Beam '02 Documentation Page
The following components should not be populated prior to mounting and wire
bonding the FPIX1 die: J7 (power connector), J8 (high voltage connector), F1
(VDDA fuse), F2 (VDDD fuse), C10, and C11.
FPIX1 Hardware
Rev 1.3 Schematic (Board Rev 1.3 same
schematic as Rev 1.1)
FPIX1_Schematic_Rev1_1.pdf
Rev 1.3 Board Layout/Mounting Hole
Locations
Layout_FPIX1_Rev1_3.jpg
Layout_FPIX1_Rev1_3.pdf
(11"x17")
Rev 1.3 Wire Bonding Diagram
WireBonding_BoardRev1_3.jpg
WireBonding_BoardRev1_3.pdf
Parts List
PartsListFPIX1innerBoard.pdf
(11"x17")
FPIX1 Documents
"FPIX1 Chip" by Sergio Zimmermann,
Jim Hoff, & Abder Mekkaoui
"FPIX1 Pad Description" by Jim Hoff (dtd
11/20/98)
"FPIX1 Digital Architecture and
Operation: Design and Simulations" by Jim Hoff (dtd 6/25/98)
"FPIX1 Wafer Tests" Guilherme
Cardoso's writeup of wafer tests done on 4 FPIX1 wafers (6/13/00 - pdf file)
Interface to PMC
Latest Interface documentation can be found in the Test Beam '02 Readout
Electronic documentation found on the ESE Test
Beam '02 Web site
FPIX1 PMC Firmware
Firmware Rev 1.8 Top Level Schematic
(03/10/03)
FPIX1_1_8_PMC_Top.pdf
Firmware Rev 1.8 Bit Streams (03/10/03)
pmc_top.mcs
pmc_top.bit
Firmware Rev 1.8 Archived Firmware
Design Files (03/10/03)
FPIX1_TestBeam_Rev1_8.zip
Archived FPIX1 PMC Firmware
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Date |
Rev |
Schematic |
Bit Streams |
Design Files |
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12/18/02 |
1.7 |
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12/11/02 |
1.6 |
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11/25/02 |
1.5 |
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09/16/02 |
1.4 |
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FPIX1 Hit Maps and Characterization
(documentation prepared by Marcos Turqueti)
Updated 03/11/03
Questions? Email: bhall@fnal.gov
