This page documents the test setup created for testing a single FPIX2 serializer chip and two SSR chips for use at the Indiana University Cyclotron Facility (IUCF) July 25 and 26, 2002.

Document describing test setup and firmware:
        PMCBERT_SerializerAndSSR_Rev1_1.doc
        PMCBERT_SerializerAndSSR_Rev1_1.pdf

Link to PMC schematic:
        .pdf

PMC FPGA Firmware Top Level Schematic:
        PMC_Top.pdf

PMC Firmware Design Files (Rev 1.1):
        FPIX2PeriphBERT.zip
 

Image of SSR board with two SSR chips (left) and FPIX Serializer board with 1 FPIX serializer (right):

 
 
 

Image of PTA and PMC in the PC with cables attached:

 
 

Jim and Gabriele at ~10:00pm 7/24/02 loading up the company van for their 270 mile trip to IUCF:

 

PMC termination resistor configuration:



Updated 08/15/02
Questions?  Email: bhall@fnal.gov

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