Prototype Test System:
The main reasons to build an Optical Link prototype system with discrete components include:

• to integrate the optical links to the five chip FPIX module being designed
• to test the conceptual design of the bi-phase mark encoded signal for FPIX initialization and control
• to test the CHFET gigabit serializer and transmitter and its sensitivity to jitter noise
• to test optical transmission and reception issues (biasing, bandwidth, optical power, etc)

Gigabit Transmitter Test Module:
The Gigabit Link is the most critical one due to the high speed and noise problems that may affect the Serializer/Transmitter chip. This gigabit transmitter will be based on a CHFET chip designed by Peter Denes (Princeton/CMS) (link to P.Denes CHFET serializer and transmiter chip). The second iteration of this chip will, probably, be available at FNAL in Nov.99. The chip, as most of very fast serializers, is affected by jitter noise and probably power supply variations. These effects will be tested with this test module and with the CHFET BERT system.
A ring-oscillator based PLL will be implemented as part of the Bi-phase Receiver module to deliver clean clocks to the CHFET chip.

Gigabit Receiver Test Module:
The Gigabit Receiver and the Bi-phase Transmitter modules will share a same physical board.
The Gigabit Receiver and the Bi-phase Transmitter module will be integrated to the test DAQ system. The test DAQ system must be able to download FPIX chip configurations, send control signals and readout the data generated by the FPIX module. Two alternatives will be analyzed for the interface:

• a test stand system similar to the existing one being used with FPIX0
• a new test stand based on a PC-LabView system

Bi-phase Transmitter Test module:
The Bi-phase Transmitter Test module will share the same board and Test Stand interface with the Gigabit Receiver module.
The Bi-phase signal and clock generator module is in charge of serializing the information, generating the bi-phase signal. This module will be implemented in an EPLD.
The bi-phase signal will modulate a VCSEL diode. The VCSEL, bias circuit and driver will be designed based on the results of existing results (link to VCSEL test results).

The Bi-phase Receiver Test Module:
The Bi-phase receiver performes the following functions:

• recovers the 53 MHz clock
• converts the input serial stream to parallel
• decodes commands and generates a proper action (FF set or reset, software reset, etc)
• generates the BCO clock

Interfaces: The Bi-phase Receiver must drive CMOS and LVDS signals to the FPIX chips. The input clock to the CHFET chip is differential PECL. We must ask P.Denes what is the electrical protocol of the other CHFET signals.

PLL:
The Phase Lock Loop must provide good frequency stability and very low noise. The output clock's jitter must be less than 100ps (0.5% of the signal's period).
 

Associated tasks:
CHFET chip Bit Error Rate Tests:
The CHFET BERT system is designed based on the SLIDAS/SLITEST/PCI system designed by Erik van der Bij at CERN. This system was designed as part of the S-Link connector test system but it can be interfaced to make a BER tester for the CHFET chip. Two personality cards will be designed to complete the BERT system: a CHFET transmitter personality card and a Low Power G-Link transmitter card.
 

VCSEL and PIN substrate:
 

VCSEL and PIN tests. Fiber Optic and Connector tests:
 
 
 
 
 

cancelo@fnal.gov