BTeV Project at Fermilab

Optical Links for BTeV Pixel Detector

Results on VCSEL testing:

Mitel 444: DC test results (for a version click here)

Honeywell 4080: DC test results (for a version click here)

Mitel 469 & 470: VCSEL and PiN array test results (for a version click here)

Pixel Plane Control and Readout Documents:

Optical Link Receiver Chip: This file gives a good background to the problem but the specification of the Optical Receiver Chip has changed. See the Optical Link Receiver presentation for the changes. I'll try to update this document ASAP.

Optical Link Receiver Presentation: (Power Point file)

Optical_Receiver_Spec: Preliminary version of the Optical Receiver chip specification.
(for a version click here). Updated June16th, 1999.

Optical Link for Pixel Control and Readout. Prototype System:

A prototype system with optical links for Pixel Control and Readout will be designed:

to integrate the optical links to the five chip FPIX module being designed
to test the conceptual design of the bi-phase mark encoded signal for FPIX initialization and control
to test the CHFET gigabit serializer and transmitter and its sensitivity to jitter noise
to test optical transmission and reception issues (biasing, bandwidth, optical power, etc)

The optical links will be integrated to the FPIX1 module Test Stand. The purpose for the Test Stand is to characterize a Pixel Detector module with 5 FPIX1 chips. Each chip contains almost 3K pixels. The Test Stand must serve two purposes: to perform a complate bench characterization of the FPIX1 module (noise, threshold, bump-bonds, etc) and as the basic DAQ system to integrate the FPIX1 module and SVXIII chips in a telescope for a beam test. A drawing of the proposed Test Stand can be found here.

The Prototype Optical Link electronics will be contained in two boards: a VME based FPIX1 control board and in the FPIX1 module Inner board. The first board will have a 53MHz optical link to deliver clock and control information to the FPIX1 module and a Gigabit Receiver Link to receive the data generated by the FPIX1 module. The Inner board will have the counterpart links, a 53MHz receiver and a Gigabit Transmitter link.

Links:
Fermilab's home page
BTeV's home page
Fermilab Computing Division / Electronic Systems Engineering projects
Fermilab Rad Hard Vertex Detector R&D
CMS ECAL (link to P.Denes CHFET serializer and transmiter chip)
ATLAS SCT (Silicon Central Tracker) links

Radiation Sdudies on Fiber Optic Components by M.Pearce et al. ReferenceNo1 , ReferenceNo2

Questions and complains:

cancelo@fnal.gov