VRB Control Logic, Receive Logic and Auxiliary Port FPGAs are Altera 8000 series components.
The Processor control, Processor I/O
port and Input Port PLDs are Altera 7064s. All devices are programmed using the Altera
MAX PLUS+ development system. The
PLD/FPGA code is written in AHDL, compiled, and the resulting Altera .ttf files are then
merged with the 60EC030 code. Flash RAMs are
used to load the PLDs when the VRB boots. Code for the Flash RAMs is produced with Crossware
Embedded Development Studio.
The Altera .ttf files are included in a C program as an array. The C program has a routine
to read the .ttf data and toggle the appropriate
bits to program the FPGAs. Flash RAM code is output from the Crossware Embedded Development
Studio as a single Motorola S-record
(.hex) file.
The Svxdaq software may be used to reprogram the Flash RAM after two of the four Flash RAM
devices (U7,U8), and four of the PLDs
(U14,U15,U101,U102) have been programmed in a stand alone device programmer.
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