VME Readout Buffer (VRB)
The VME Readout Buffer (VRB) is an intelligent two stage (10-channel) buffer memory module that conforms to the VIPA Standard for a single-width 9U x 400mm module. Refer to the simplified block diagram of the VRB for the following discussion. The input stage consist of ten 64-Kbyte partitional buffer memories and the output stage appears as one 16-Kbyte FIFO to the VME interface. Accepted input data must be transferred (or scanned) to the output FIFO prior to a VME readout. The VRB input data rate from the ten (byte-wide) channel transition module is approximately 500 MBytes/sec (aggregate) with a maximum buffer depth of 64-Kbytes. The output stage readout rate is limited by the transfer speed of VME and the number of modules sharing the bus. Therefore, a significant buffer rejection ratio is assumed between the input and output stages for optimal use of the VRB buffers. Also, the VRB buffer memory is partitionable, allowing a trade-off between buffer size and number of buffers. The VRB buffer management and its control are typically delegated to a System Controller module via the transition card connector (P5, P6). However, it is possible via firmware to provide internal VRB buffer management and control. The SVX-II application implements the Silicon Readout Controller (SRC) for its buffer management and control.
Additional Technical Information
Additional Technical Information (PDF Format)
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