VME Readout Buffer (VRB)

Features
  • Single Width 9U x 400mm VME64x/VIPA Module.
  • Slave Interface Supports D32 Block Transfer Rate Up to 40 MBytes/sec
    • Conforms to VME 64 Draft Specifications, Rev. 11.1.
  • External Buffer Management and Status Monitoring via P5/6 connector.
  • Re-Programmable Logic Supports Multiple (or Moving Target) Applications
  • Supports True Simultaneous Buffer Memory Reads & Writes
  • 10 Channel (53 MBytes/sec 8-bit) TTL Port  on Rear Connector
    • Optical 4-Ch (1.5 Gb/s )G-Link Transition Module or
    • Optical 10-Channel 175Mb/s TAXI Transition Module
  • Programmable Number of Buffers & Buffer Size per Channel
    • 64-Buffers x 1-Kbytes  . . . 1-Buffer x 64-Kbytes

Description

The VME Readout Buffer (VRB) is an intelligent  two stage (10-channel) buffer memory module that conforms to the VIPA Standard for a single-width 9U x 400mm module. Refer to the simplified block diagram of the VRB for  the following discussion. The input stage consist of ten 64-Kbyte partitional buffer memories and the output stage appears as one 16-Kbyte FIFO to the VME interface. Accepted input data must be transferred (or scanned) to the output FIFO prior to a VME readout. The VRB input data rate from the ten (byte-wide) channel transition module is approximately 500 MBytes/sec (aggregate) with a maximum buffer depth of 64-Kbytes. The output stage readout rate is limited by the transfer speed of VME and the number of modules sharing the bus. Therefore, a significant buffer rejection ratio is assumed between the input and output stages for optimal use of the VRB buffers. Also, the VRB buffer memory is partitionable, allowing a trade-off between buffer size and number of buffers. The VRB buffer management and its control are typically delegated to a System Controller module via the transition card connector (P5, P6). However, it is possible via firmware to provide internal VRB buffer management and control. The SVX-II application implements the Silicon Readout Controller (SRC) for its buffer management and control.


Additional Technical Information

Block Diagram

Applications

Detail Picture

Project Schedule

Firmware

 Module Log

Additional Technical Information (PDF Format)
Specification Schematic  Parts List PC Fabrication PC Artwork Assembly Stiffener Front Panel